1. Field of the Invention
The present invention relates to an AD converter for converting analog signals into digital signals of a predetermined number of bits and for outputting the digital signals, and relates to a display unit.
2. Description of Related Art
In a display unit, such as a television, analog signals picked up by an image pickup device, such as a charge coupled device (hereinafter referred to as CCD), are converted to digitized image signals by an AD converter, and an image is displayed based on the digitized image signals. As an AD converter for digitizing analog image signals in a display unit, a parallel AD converter is generally used, which is configured to collectively compare reference voltages of different voltage values with analog input voltages.
In case of displaying an image whose contrast is low, such as an overall dark image, digital image signals after AD conversion are subjected to image correction, such as contrast adjustment. Further, image analysis, such as histogram analysis, is carried out for the digital image signals after the AD conversion, and based on the results of the analysis, image correction is controlled. In performing the contrast adjustment, a quantization width (voltage corresponding to 1 bit) for digital image signals falling in contrast-enhancing ranges is expanded, and a quantization width for digital image signals falling in other ranges is narrowed according to the contents of control that has been determined based on the image analysis. Thus, in case an AD converter imparting all ranges with an equal quantization width, or having linear characteristics, is used in digitizing image signals, a quantization width for the image signals provided with the contrast adjustment and falling within the contrast-enhancing ranges is expanded. As a result, qualities of an image displayed on the display unit are deteriorated. In order to avoid this, as disclosed in Japanese Patent Laid-Open No. 2004-048327, an AD converter having nonlinear characteristics is used, which performs digitization of image signals in such a way as to make narrower a quantization width for the image signals within the contrast-enhancing regions than that of other ranges.
The AD converter described in Japanese Patent Laid-Open No. 2004-048327 includes: a series of resistors in which a plurality of resistors are connected in series with a predetermined reference voltage applied to both ends thereof, the reference voltage being divided at connecting points between the individual resistors to produce a plurality of reference signals; a plurality of comparators for comparing voltages of the plurality of reference signals with voltages of analog image signals for conversion into comparison output signals of either a logic “0” or a logic “1”; and an encoder for outputting digital image signals (digital codes) of a predetermined number of bits based on the comparison output signals which are outputted from the comparators. In the AD converter mentioned above, a resistance of each resistor in the series of resistors is differentiated from the others to differentiate at each resistor an amount of voltage, or a quantization width, for convertible analog image signals, so that nonlinear characteristics are realized.
In the AD converter described in Japanese Patent Laid-Open No. 2004-048327, conversion characteristics are fixedly set in advance because the resistance of each resistor in the series of resistors is fixed. On the other hand, an expansion rate for the digital signals in the contrast-enhancing ranges in performing contrast adjustment is changed according to characteristics or the like of analog image signals as inputted. Under such circumstances, a problem has been raised that a mismatch occurs between a quantization width required for the contrast-enhancing ranges at the time of performing contrast adjustment, and a quantization width at the time of performing actual digital conversion.